Tuesday, November 24, 2009

100-cores by next year

Once again, hardware is far ahead of software. Tilera has announced a 100-cores processor for 2010.

Unlike standard multi-core processors, Tilera's TILE-Gx is architectured around a 2D grid network rather than a single shared bus. This is a way to jump over the "memory wall", and feed enough data to keep all cores busy.

This design provides a lot of raw computing power, but also better efficiency (more computing power per watt).

But this beast is supposed to be coded in standard C/C++. It already requires black magic in order to write a 2-threads program that behaves as expected, what about 100's of threads ?

The TILE-Gx is a perfect match for Ateji Parallel Extensions : data parallelism handles large scientific computations task parallelism handles server-like applications, and message-passing leverages the hardware's packet network interconnection mechanism. High-performance code can be arranged in a data-flow or streaming architecture, reducing accesses to shared memory.